Semiconductor devices incorporating superjunction structure to achieve improved electrical characteristics are known. For example, metal oxide semiconductor field effect transistor (MOSFET) devices can be incorporated with vertical or horizontal superjunction structure to optimize the on-resistance and the breakdown voltage characteristics of the transistor. As an example, Fujihira describes configurations of the lateral and vertical superjunction devices in the paper entitled “Theory of Semiconductor Superjunction Devices” (Japan Journal of Applied Physics Vol. 36, October 1997, pp. 6254-6262).
More specifically, superjunction transistors provide a way to achieve low on-resistance (Rds-on), while maintaining a high off-state breakdown voltage (BV). Superjunction devices include alternating P-type and N-type doped columns formed in the drift region. In the OFF-state of the MOSFET, the columns are completely depleted at relatively low voltage and thus can sustain a high breakdown voltage. For example, for a vertical superjunction structure, the columns deplete laterally, so that the entire p and n columns are depleted. For a superjunction device, the on-resistance Rds-on increases in direct proportion to the breakdown voltage BV, which is a much less dramatic increase as compared to the conventional semiconductor structure. A superjunction device may therefore have significantly lower on-resistance Rds-on than a conventional MOSFET device for the same high breakdown voltage. Conversely, a superjunction device may have a significantly higher BV than a conventional MOSFET for a given on-resistance Rds-on.
Example superjunction devices are described in various U.S. patents and literatures. FIG. 1 duplicates FIG. 29 of U.S. Pat. No. 7,002,205 which illustrates the cross-sectional view of part of an active cell portion of an exemplary superjunction device. Referring to FIG. 1, a vertical MOSFET device (e.g., an N-channel MOSFET) is formed on a suitably doped (e.g., N+) substrate 11, which acts as a drain region with a drain contact 18. A suitably-doped semiconductor layer (e.g., an N-Epitaxial layer) is formed on top of the substrate 11. The MOSFET device also includes a P-body region 13, an N+ source region 14, and an N+ polysilicon gate region 16, separated from the N-Epitaxial layer and the body region by a gate oxide layer 15. The MOSFET device also includes a gate contact (not shown) and a source metal 17. The source metal 27 connects electrically to the source region 14 and a heavily doped P+ body contact region 19. A superjunction structure 22 is formed in the N-Epitaxial layer and includes alternating, charge balanced P-type columns 22b and N-type columns 22a. The P-type and N-type columns are completely depleted horizontally at a low voltage and so are able to withstand a high breakdown voltage in the vertical direction. In some example, the P-type columns 22b maybe formed by implantation of P-type dopants into the N-type Epitaxial layer and the N-type columns 22a may be formed by portions of the N-type epitaxial layer that are situated adjacent to the P-type columns 22b. 
In a power semiconductor device, termination techniques are employed to mitigate the high electrical field that may develop at the end or the termination of the active cell regions of the semiconductor device. A power semiconductor device includes a core region in which active transistor cells are formed and a termination region that encircles the core region. The termination region typically includes edge termination regions and corner regions. In a superjunction power semiconductor device, charge needs to be balanced everywhere, including the corner and termination regions. In the core region, the P columns can be arranged in uniform parallel rows, making it simple to achieve the charge balance. However, at the edge termination regions and the corner regions, it is more difficult to achieve charge balance. In particular, in the core region, the charge balance is two-dimensional as the P and N columns are formed in parallel rows. However, in the corner region, the charge balance becomes three-dimensional because of the curvature of the curved P and N columns. When charge balance is not maintained, the breakdown voltage (BV) of the semiconductor device decreases and the device becomes less robust. Maintaining charge balance in the termination region at the corners or edges of the power semiconductor device remains challenging.